commit 0af017aef8e3798ed0adb0b051a3a2cbbcf23072
Author: Kyle Milz <krwmilz@gmail.com>
Date: Thu, 18 Nov 2021 00:35:08 +0000
import pll fix for RV770 on openbsd
Diffstat:
10 files changed, 1030 insertions(+), 0 deletions(-)
diff --git a/imac_radeondrm_atombios_encoders.diff b/imac_radeondrm_atombios_encoders.diff
@@ -0,0 +1,41 @@
+Index: radeon/atombios_encoders.c
+===================================================================
+RCS file: /cvs/src/sys/dev/pci/drm/radeon/atombios_encoders.c,v
+retrieving revision 1.14
+diff -u -p -r1.14 atombios_encoders.c
+--- radeon/atombios_encoders.c 14 Apr 2019 10:14:53 -0000 1.14
++++ radeon/atombios_encoders.c 18 Oct 2020 18:57:59 -0000
+@@ -2191,12 +2191,13 @@ int radeon_atom_pick_dig_encoder(struct
+ }
+
+ /*
+- * On DCE32 any encoder can drive any block so usually just use crtc id,
+- * but Apple thinks different at least on iMac10,1, so there use linkb,
+- * otherwise the internal eDP panel will stay dark.
++ * On DCE31 any encoder can drive any block so usually just use crtc id,
++ * but Apple thinks different at least on iMac10,1 and iMac11,1, so
++ * there use linkb, otherwise the internal eDP panel will stay dark.
+ */
+- if (ASIC_IS_DCE32(rdev)) {
+- if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1"))
++ if (ASIC_IS_DCE31(rdev)) {
++ if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1") ||
++ dmi_match(DMI_PRODUCT_NAME, "iMac11,1"))
+ enc_idx = (dig->linkb) ? 1 : 0;
+ else
+ enc_idx = radeon_crtc->crtc_id;
+Index: radeon/radeon.h
+===================================================================
+RCS file: /cvs/src/sys/dev/pci/drm/radeon/radeon.h,v
+retrieving revision 1.23
+diff -u -p -r1.23 radeon.h
+--- radeon/radeon.h 4 May 2019 11:34:48 -0000 1.23
++++ radeon/radeon.h 18 Oct 2020 18:57:59 -0000
+@@ -2687,6 +2687,7 @@ void r100_pll_errata_after_index(struct
+ (rdev->family == CHIP_RS740) || \
+ (rdev->family >= CHIP_R600))
+ #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
++#define ASIC_IS_DCE31(rdev) ((rdev->family >= CHIP_RV770))
+ #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
+ #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
+ #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
diff --git a/imac_radeondrm_delay.diff b/imac_radeondrm_delay.diff
@@ -0,0 +1,16 @@
+Index: include/linux/delay.h
+===================================================================
+RCS file: /cvs/src/sys/dev/pci/drm/include/linux/delay.h,v
+retrieving revision 1.1
+diff -u -p -r1.1 delay.h
+--- include/linux/delay.h 14 Apr 2019 10:14:53 -0000 1.1
++++ include/linux/delay.h 18 Oct 2020 18:57:59 -0000
+@@ -20,7 +20,7 @@ ndelay(unsigned long nsecs)
+ static inline void
+ usleep_range(unsigned long min, unsigned long max)
+ {
+- DELAY(min);
++ DELAY((min + max) / 2);
+ }
+
+ static inline void
diff --git a/imac_radeondrm_display.diff b/imac_radeondrm_display.diff
@@ -0,0 +1,338 @@
+Index: radeon/radeon_display.c
+===================================================================
+RCS file: /cvs/src/sys/dev/pci/drm/radeon/radeon_display.c,v
+retrieving revision 1.19
+diff -u -p -r1.19 radeon_display.c
+--- radeon/radeon_display.c 27 Feb 2020 05:34:13 -0000 1.19
++++ radeon/radeon_display.c 18 Oct 2020 18:57:59 -0000
+@@ -37,8 +37,6 @@
+ #include <drm/drm_plane_helper.h>
+ #include <drm/drm_edid.h>
+
+-#include <linux/gcd.h>
+-
+ static void avivo_crtc_load_lut(struct drm_crtc *crtc)
+ {
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+@@ -865,89 +863,66 @@ static bool radeon_setup_enc_conn(struct
+ }
+
+ /* avivo */
++static void avivo_get_fb_div(struct radeon_pll *pll,
++ u32 target_clock,
++ u32 post_div,
++ u32 ref_div,
++ u32 *fb_div,
++ u32 *frac_fb_div)
++{
++ u32 tmp = post_div * ref_div;
++
++ tmp *= target_clock;
++ *fb_div = tmp / pll->reference_freq;
++ *frac_fb_div = tmp % pll->reference_freq;
++
++ if (*fb_div > pll->max_feedback_div)
++ *fb_div = pll->max_feedback_div;
++ else if (*fb_div < pll->min_feedback_div)
++ *fb_div = pll->min_feedback_div;
++}
++
++static u32 avivo_get_post_div(struct radeon_pll *pll,
++ u32 target_clock)
++{
++ u32 vco, post_div, tmp;
++
++ if (pll->flags & RADEON_PLL_USE_POST_DIV)
++ return pll->post_div;
++
++ if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
++ if (pll->flags & RADEON_PLL_IS_LCD)
++ vco = pll->lcd_pll_out_min;
++ else
++ vco = pll->pll_out_min;
++ } else {
++ if (pll->flags & RADEON_PLL_IS_LCD)
++ vco = pll->lcd_pll_out_max;
++ else
++ vco = pll->pll_out_max;
++ }
+
+-/**
+- * avivo_reduce_ratio - fractional number reduction
+- *
+- * @nom: nominator
+- * @den: denominator
+- * @nom_min: minimum value for nominator
+- * @den_min: minimum value for denominator
+- *
+- * Find the greatest common divisor and apply it on both nominator and
+- * denominator, but make nominator and denominator are at least as large
+- * as their minimum values.
+- */
+-static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
+- unsigned nom_min, unsigned den_min)
+-{
+- unsigned tmp;
+-
+- /* reduce the numbers to a simpler ratio */
+- tmp = gcd(*nom, *den);
+- *nom /= tmp;
+- *den /= tmp;
+-
+- /* make sure nominator is large enough */
+- if (*nom < nom_min) {
+- tmp = DIV_ROUND_UP(nom_min, *nom);
+- *nom *= tmp;
+- *den *= tmp;
+- }
+-
+- /* make sure the denominator is large enough */
+- if (*den < den_min) {
+- tmp = DIV_ROUND_UP(den_min, *den);
+- *nom *= tmp;
+- *den *= tmp;
++ post_div = vco / target_clock;
++ tmp = vco % target_clock;
++
++ if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
++ if (tmp)
++ post_div++;
++ } else {
++ if (!tmp)
++ post_div--;
+ }
+-}
+
+-/**
+- * avivo_get_fb_ref_div - feedback and ref divider calculation
+- *
+- * @nom: nominator
+- * @den: denominator
+- * @post_div: post divider
+- * @fb_div_max: feedback divider maximum
+- * @ref_div_max: reference divider maximum
+- * @fb_div: resulting feedback divider
+- * @ref_div: resulting reference divider
+- *
+- * Calculate feedback and reference divider for a given post divider. Makes
+- * sure we stay within the limits.
+- */
+-static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
+- unsigned fb_div_max, unsigned ref_div_max,
+- unsigned *fb_div, unsigned *ref_div)
+-{
+- /* limit reference * post divider to a maximum */
+- ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
++ if (post_div > pll->max_post_div)
++ post_div = pll->max_post_div;
++ else if (post_div < pll->min_post_div)
++ post_div = pll->min_post_div;
+
+- /* get matching reference and feedback divider */
+- *ref_div = min(max(den/post_div, 1u), ref_div_max);
+- *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
+-
+- /* limit fb divider to its maximum */
+- if (*fb_div > fb_div_max) {
+- *ref_div = (*ref_div * fb_div_max)/(*fb_div);
+- *fb_div = fb_div_max;
+- }
++ return post_div;
+ }
+
+-/**
+- * radeon_compute_pll_avivo - compute PLL paramaters
+- *
+- * @pll: information about the PLL
+- * @dot_clock_p: resulting pixel clock
+- * fb_div_p: resulting feedback divider
+- * frac_fb_div_p: fractional part of the feedback divider
+- * ref_div_p: resulting reference divider
+- * post_div_p: resulting reference divider
+- *
+- * Try to calculate the PLL parameters to generate the given frequency:
+- * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
+- */
++#define MAX_TOLERANCE 10
++
+ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ u32 freq,
+ u32 *dot_clock_p,
+@@ -956,138 +931,55 @@ void radeon_compute_pll_avivo(struct rad
+ u32 *ref_div_p,
+ u32 *post_div_p)
+ {
+- unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
+- freq : freq / 10;
+-
+- unsigned fb_div_min, fb_div_max, fb_div;
+- unsigned post_div_min, post_div_max, post_div;
+- unsigned ref_div_min, ref_div_max, ref_div;
+- unsigned post_div_best, diff_best;
+- unsigned nom, den;
++ u32 target_clock = freq / 10;
++ u32 post_div = avivo_get_post_div(pll, target_clock);
++ u32 ref_div = pll->min_ref_div;
++ u32 fb_div = 0, frac_fb_div = 0, tmp;
+
+- /* determine allowed feedback divider range */
+- fb_div_min = pll->min_feedback_div;
+- fb_div_max = pll->max_feedback_div;
+-
+- if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
+- fb_div_min *= 10;
+- fb_div_max *= 10;
+- }
+-
+- /* determine allowed ref divider range */
+ if (pll->flags & RADEON_PLL_USE_REF_DIV)
+- ref_div_min = pll->reference_div;
+- else
+- ref_div_min = pll->min_ref_div;
+-
+- if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
+- pll->flags & RADEON_PLL_USE_REF_DIV)
+- ref_div_max = pll->reference_div;
+- else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
+- /* fix for problems on RS880 */
+- ref_div_max = min(pll->max_ref_div, 7u);
+- else
+- ref_div_max = pll->max_ref_div;
+-
+- /* determine allowed post divider range */
+- if (pll->flags & RADEON_PLL_USE_POST_DIV) {
+- post_div_min = pll->post_div;
+- post_div_max = pll->post_div;
+- } else {
+- unsigned vco_min, vco_max;
+-
+- if (pll->flags & RADEON_PLL_IS_LCD) {
+- vco_min = pll->lcd_pll_out_min;
+- vco_max = pll->lcd_pll_out_max;
+- } else {
+- vco_min = pll->pll_out_min;
+- vco_max = pll->pll_out_max;
+- }
++ ref_div = pll->reference_div;
+
+- if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
+- vco_min *= 10;
+- vco_max *= 10;
++ if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
++ avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div,
++ &frac_fb_div);
++ frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
++ if (frac_fb_div >= 5) {
++ frac_fb_div -= 5;
++ frac_fb_div = frac_fb_div / 10;
++ frac_fb_div++;
+ }
+
+- post_div_min = vco_min / target_clock;
+- if ((target_clock * post_div_min) < vco_min)
+- ++post_div_min;
+- if (post_div_min < pll->min_post_div)
+- post_div_min = pll->min_post_div;
+-
+- post_div_max = vco_max / target_clock;
+- if ((target_clock * post_div_max) > vco_max)
+- --post_div_max;
+- if (post_div_max > pll->max_post_div)
+- post_div_max = pll->max_post_div;
+- }
+-
+- /* represent the searched ratio as fractional number */
+- nom = target_clock;
+- den = pll->reference_freq;
+-
+- /* reduce the numbers to a simpler ratio */
+- avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
+-
+- /* now search for a post divider */
+- if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
+- post_div_best = post_div_min;
+- else
+- post_div_best = post_div_max;
+- diff_best = ~0;
+-
+- for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
+- unsigned diff;
+- avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
+- ref_div_max, &fb_div, &ref_div);
+- diff = abs(target_clock - (pll->reference_freq * fb_div) /
+- (ref_div * post_div));
+-
+- if (diff < diff_best || (diff == diff_best &&
+- !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
+-
+- post_div_best = post_div;
+- diff_best = diff;
++ if (frac_fb_div >= 10) {
++ fb_div++;
++ frac_fb_div = 0;
+ }
+- }
+- post_div = post_div_best;
+-
+- /* get the feedback and reference divider for the optimal value */
+- avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
+- &fb_div, &ref_div);
+-
+- /* reduce the numbers to a simpler ratio once more */
+- /* this also makes sure that the reference divider is large enough */
+- avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
+-
+- /* avoid high jitter with small fractional dividers */
+- if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
+- fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
+- if (fb_div < fb_div_min) {
+- unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
+- fb_div *= tmp;
+- ref_div *= tmp;
+- }
+- }
+-
+- /* and finally save the result */
+- if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
+- *fb_div_p = fb_div / 10;
+- *frac_fb_div_p = fb_div % 10;
+ } else {
+- *fb_div_p = fb_div;
+- *frac_fb_div_p = 0;
+- }
+-
+- *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
+- (pll->reference_freq * *frac_fb_div_p)) /
+- (ref_div * post_div * 10);
++ while (ref_div <= pll->max_ref_div) {
++ avivo_get_fb_div(pll, target_clock, post_div, ref_div,
++ &fb_div, &frac_fb_div);
++ if (frac_fb_div >= (pll->reference_freq / 2))
++ fb_div++;
++ frac_fb_div = 0;
++ tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
++ tmp = (tmp * 10000) / target_clock;
++
++ if (tmp > (10000 + MAX_TOLERANCE))
++ ref_div++;
++ else if (tmp >= (10000 - MAX_TOLERANCE))
++ break;
++ else
++ ref_div++;
++ }
++ }
++
++ *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) / (ref_div * post_div * 10);
++ *fb_div_p = fb_div;
++ *frac_fb_div_p = frac_fb_div;
+ *ref_div_p = ref_div;
+ *post_div_p = post_div;
+
+- DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
+- freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
+- ref_div, post_div);
++ DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
++ *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
+ }
+
+ /* pre-avivo */
diff --git a/orig/pll_1.diff b/orig/pll_1.diff
@@ -0,0 +1,33 @@
+commit 72edd83cc9e5819ed1ee771519143d7594e059f0
+Author: Christian König <christian.koenig@amd.com>
+Date: Thu Jan 29 16:01:03 2015 +0100
+
+ drm/radeon: fix PLLs on RS880 and older v2
+
+ This is a workaround for RS880 and older chips which seem to have
+ an additional limit on the minimum PLL input frequency.
+
+ v2: fix signed/unsigned warning
+
+ bugs:
+ https://bugzilla.kernel.org/show_bug.cgi?id=91861
+ https://bugzilla.kernel.org/show_bug.cgi?id=83461
+
+ Signed-off-by: Christian König <christian.koenig@amd.com>
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+ Cc: stable@vger.kernel.org
+
+diff --git b/drivers/gpu/drm/radeon/radeon_display.c a/drivers/gpu/drm/radeon/radeon_display.c
+index 913fafa597ad..102116902a07 100644
+--- b/drivers/gpu/drm/radeon/radeon_display.c
++++ a/drivers/gpu/drm/radeon/radeon_display.c
+@@ -960,9 +960,6 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
+ pll->flags & RADEON_PLL_USE_REF_DIV)
+ ref_div_max = pll->reference_div;
+- else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
+- /* fix for problems on RS880 */
+- ref_div_max = min(pll->max_ref_div, 7u);
+ else
+ ref_div_max = pll->max_ref_div;
+
diff --git a/orig/pll_2.diff b/orig/pll_2.diff
@@ -0,0 +1,25 @@
+commit 4b21ce1b4b5d262e7d4656b8ececc891fc3cb806
+Author: Christian König <christian.koenig@amd.com>
+Date: Wed May 21 15:25:41 2014 +0200
+
+ drm/radeon: lower the ref * post PLL maximum once more
+
+ Let's be conservative and use 100 here until we find something better.
+
+ Bugs: https://bugzilla.kernel.org/show_bug.cgi?id=75241
+
+ Signed-off-by: Christian König <christian.koenig@amd.com>
+
+diff --git b/drivers/gpu/drm/radeon/radeon_display.c a/drivers/gpu/drm/radeon/radeon_display.c
+index 356b733caafe..f00dbbf4d806 100644
+--- b/drivers/gpu/drm/radeon/radeon_display.c
++++ a/drivers/gpu/drm/radeon/radeon_display.c
+@@ -862,7 +862,7 @@ static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
+ unsigned *fb_div, unsigned *ref_div)
+ {
+ /* limit reference * post divider to a maximum */
+- ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
++ ref_div_max = min(128 / post_div, ref_div_max);
+
+ /* get matching reference and feedback divider */
+ *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
diff --git a/orig/pll_3.diff b/orig/pll_3.diff
@@ -0,0 +1,46 @@
+commit 3b333c55485fef0089ae7398906599d000df195e
+Author: Christian König <christian.koenig@amd.com>
+Date: Thu Apr 24 18:39:59 2014 +0200
+
+ drm/radeon: avoid high jitter with small frac divs
+
+ Signed-off-by: Christian König <christian.koenig@amd.com>
+
+diff --git b/drivers/gpu/drm/radeon/radeon_display.c a/drivers/gpu/drm/radeon/radeon_display.c
+index 9ff0e2f1be6a..14bd701e316c 100644
+--- b/drivers/gpu/drm/radeon/radeon_display.c
++++ a/drivers/gpu/drm/radeon/radeon_display.c
+@@ -830,14 +830,14 @@ static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
+
+ /* make sure nominator is large enough */
+ if (*nom < nom_min) {
+- tmp = DIV_ROUND_UP(nom_min, *nom);
++ tmp = (nom_min + *nom - 1) / *nom;
+ *nom *= tmp;
+ *den *= tmp;
+ }
+
+ /* make sure the denominator is large enough */
+ if (*den < den_min) {
+- tmp = DIV_ROUND_UP(den_min, *den);
++ tmp = (den_min + *den - 1) / *den;
+ *nom *= tmp;
+ *den *= tmp;
+ }
+@@ -997,16 +997,6 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ /* this also makes sure that the reference divider is large enough */
+ avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
+
+- /* avoid high jitter with small fractional dividers */
+- if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
+- fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60);
+- if (fb_div < fb_div_min) {
+- unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
+- fb_div *= tmp;
+- ref_div *= tmp;
+- }
+- }
+-
+ /* and finally save the result */
+ if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
+ *fb_div_p = fb_div / 10;
diff --git a/orig/pll_4.diff b/orig/pll_4.diff
@@ -0,0 +1,148 @@
+commit c2fb3094669a3205f16a32f4119d0afe40b1a1fd
+Author: Christian König <christian.koenig@amd.com>
+Date: Sun Apr 20 13:24:32 2014 +0200
+
+ drm/radeon: improve PLL limit handling in post div calculation
+
+ This improves the PLL parameters when we work at
+ the limits of the allowed ranges.
+
+ Signed-off-by: Christian König <christian.koenig@amd.com>
+
+diff --git b/drivers/gpu/drm/radeon/radeon_display.c a/drivers/gpu/drm/radeon/radeon_display.c
+index 8d99d5ee8014..e6c3c5488259 100644
+--- b/drivers/gpu/drm/radeon/radeon_display.c
++++ a/drivers/gpu/drm/radeon/radeon_display.c
+@@ -839,38 +839,6 @@ static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
+ }
+ }
+
+-/**
+- * avivo_get_fb_ref_div - feedback and ref divider calculation
+- *
+- * @nom: nominator
+- * @den: denominator
+- * @post_div: post divider
+- * @fb_div_max: feedback divider maximum
+- * @ref_div_max: reference divider maximum
+- * @fb_div: resulting feedback divider
+- * @ref_div: resulting reference divider
+- *
+- * Calculate feedback and reference divider for a given post divider. Makes
+- * sure we stay within the limits.
+- */
+-static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
+- unsigned fb_div_max, unsigned ref_div_max,
+- unsigned *fb_div, unsigned *ref_div)
+-{
+- /* limit reference * post divider to a maximum */
+- ref_div_max = min(210 / post_div, ref_div_max);
+-
+- /* get matching reference and feedback divider */
+- *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
+- *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
+-
+- /* limit fb divider to its maximum */
+- if (*fb_div > fb_div_max) {
+- *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
+- *fb_div = fb_div_max;
+- }
+-}
+-
+ /**
+ * radeon_compute_pll_avivo - compute PLL paramaters
+ *
+@@ -892,9 +860,6 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ u32 *ref_div_p,
+ u32 *post_div_p)
+ {
+- unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
+- freq : freq / 10;
+-
+ unsigned fb_div_min, fb_div_max, fb_div;
+ unsigned post_div_min, post_div_max, post_div;
+ unsigned ref_div_min, ref_div_max, ref_div;
+@@ -927,6 +892,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ post_div_min = pll->post_div;
+ post_div_max = pll->post_div;
+ } else {
++ unsigned target_clock = freq / 10;
+ unsigned vco_min, vco_max;
+
+ if (pll->flags & RADEON_PLL_IS_LCD) {
+@@ -937,11 +903,6 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ vco_max = pll->pll_out_max;
+ }
+
+- if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
+- vco_min *= 10;
+- vco_max *= 10;
+- }
+-
+ post_div_min = vco_min / target_clock;
+ if ((target_clock * post_div_min) < vco_min)
+ ++post_div_min;
+@@ -956,7 +917,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ }
+
+ /* represent the searched ratio as fractional number */
+- nom = target_clock;
++ nom = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? freq : freq / 10;
+ den = pll->reference_freq;
+
+ /* reduce the numbers to a simpler ratio */
+@@ -970,12 +931,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ diff_best = ~0;
+
+ for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
+- unsigned diff;
+- avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
+- ref_div_max, &fb_div, &ref_div);
+- diff = abs(target_clock - (pll->reference_freq * fb_div) /
+- (ref_div * post_div));
+-
++ unsigned diff = abs(den - den / post_div * post_div);
+ if (diff < diff_best || (diff == diff_best &&
+ !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
+
+@@ -985,9 +941,28 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ }
+ post_div = post_div_best;
+
+- /* get the feedback and reference divider for the optimal value */
+- avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
+- &fb_div, &ref_div);
++ /* limit reference * post divider to a maximum */
++ ref_div_max = min(210 / post_div, ref_div_max);
++
++ /* get matching reference and feedback divider */
++ ref_div = max(DIV_ROUND_CLOSEST(den, post_div), 1u);
++ fb_div = DIV_ROUND_CLOSEST(nom * ref_div * post_div, den);
++
++ /* we're almost done, but reference and feedback
++ divider might be to large now */
++
++ nom = fb_div;
++ den = ref_div;
++
++ if (fb_div > fb_div_max) {
++ ref_div = DIV_ROUND_CLOSEST(den * fb_div_max, nom);
++ fb_div = fb_div_max;
++ }
++
++ if (ref_div > ref_div_max) {
++ ref_div = ref_div_max;
++ fb_div = DIV_ROUND_CLOSEST(nom * ref_div_max, den);
++ }
+
+ /* reduce the numbers to a simpler ratio once more */
+ /* this also makes sure that the reference divider is large enough */
+@@ -1009,7 +984,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ *post_div_p = post_div;
+
+ DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
+- freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
++ freq, *dot_clock_p, *fb_div_p, *frac_fb_div_p,
+ ref_div, post_div);
+ }
+
diff --git a/orig/pll_5.diff b/orig/pll_5.diff
@@ -0,0 +1,26 @@
+commit 24315814239a3fdb306244c99bd076bc79db4ade
+Author: Christian König <christian.koenig@amd.com>
+Date: Sat Apr 19 18:57:14 2014 +0200
+
+ drm/radeon: use fixed PPL ref divider if needed
+
+ Signed-off-by: Christian König <christian.koenig@amd.com>
+
+diff --git b/drivers/gpu/drm/radeon/radeon_display.c a/drivers/gpu/drm/radeon/radeon_display.c
+index e6c3c5488259..2f7cbb901fb1 100644
+--- b/drivers/gpu/drm/radeon/radeon_display.c
++++ a/drivers/gpu/drm/radeon/radeon_display.c
+@@ -880,12 +880,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ ref_div_min = pll->reference_div;
+ else
+ ref_div_min = pll->min_ref_div;
+-
+- if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
+- pll->flags & RADEON_PLL_USE_REF_DIV)
+- ref_div_max = pll->reference_div;
+- else
+- ref_div_max = pll->max_ref_div;
++ ref_div_max = pll->max_ref_div;
+
+ /* determine allowed post divider range */
+ if (pll->flags & RADEON_PLL_USE_POST_DIV) {
diff --git a/orig/pll_6.diff b/orig/pll_6.diff
@@ -0,0 +1,54 @@
+commit f8a2645ecede4eaf90b3d785f2805c8ecb76d43e
+Author: Christian König <christian.koenig@amd.com>
+Date: Wed Apr 16 11:54:21 2014 +0200
+
+ drm/radeon: improve PLL params if we don't match exactly v2
+
+ Otherwise we might be quite off on older chipsets.
+
+ v2: keep ref_div minimum
+
+ Signed-off-by: Christian König <christian.koenig@amd.com>
+
+diff --git b/drivers/gpu/drm/radeon/radeon_display.c a/drivers/gpu/drm/radeon/radeon_display.c
+index 063d4255137f..2f42912031ac 100644
+--- b/drivers/gpu/drm/radeon/radeon_display.c
++++ a/drivers/gpu/drm/radeon/radeon_display.c
+@@ -865,7 +865,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ unsigned post_div_min, post_div_max, post_div;
+ unsigned ref_div_min, ref_div_max, ref_div;
+ unsigned post_div_best, diff_best;
+- unsigned nom, den;
++ unsigned nom, den, tmp;
+
+ /* determine allowed feedback divider range */
+ fb_div_min = pll->min_feedback_div;
+@@ -941,23 +941,22 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ ref_div_max = min(210 / post_div, ref_div_max);
+
+ /* get matching reference and feedback divider */
+- ref_div = max(DIV_ROUND_CLOSEST(den, post_div), 1u);
+- fb_div = DIV_ROUND_CLOSEST(nom * ref_div * post_div, den);
++ ref_div = max(den / post_div, 1u);
++ fb_div = nom;
+
+ /* we're almost done, but reference and feedback
+ divider might be to large now */
+
+- nom = fb_div;
+- den = ref_div;
++ tmp = ref_div;
+
+ if (fb_div > fb_div_max) {
+- ref_div = DIV_ROUND_CLOSEST(den * fb_div_max, nom);
++ ref_div = ref_div * fb_div_max / fb_div;
+ fb_div = fb_div_max;
+ }
+
+ if (ref_div > ref_div_max) {
+ ref_div = ref_div_max;
+- fb_div = DIV_ROUND_CLOSEST(nom * ref_div_max, den);
++ fb_div = nom * ref_div_max / tmp;
+ }
+
+ /* reduce the numbers to a simpler ratio once more */
diff --git a/orig/pll_7.diff b/orig/pll_7.diff
@@ -0,0 +1,303 @@
+commit 32167016076f714f0e35e287fbead7de0f1fb179
+Author: Christian König <christian.koenig@amd.com>
+Date: Fri Mar 28 18:55:10 2014 +0100
+
+ drm/radeon: rework finding display PLL numbers v2
+
+ This completely reworks how the PLL parameters are generated and
+ should result in better matching dot clock frequencies.
+
+ Probably needs quite a bit of testing.
+
+ bugs: https://bugs.freedesktop.org/show_bug.cgi?id=76564
+
+ v2: more cleanup and comments.
+
+ Signed-off-by: Christian König <christian.koenig@amd.com>
+ Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+
+diff --git b/drivers/gpu/drm/radeon/radeon_display.c a/drivers/gpu/drm/radeon/radeon_display.c
+index 63d54ef758fc..5701fbb36b3c 100644
+--- b/drivers/gpu/drm/radeon/radeon_display.c
++++ a/drivers/gpu/drm/radeon/radeon_display.c
+@@ -34,8 +34,6 @@
+ #include <drm/drm_crtc_helper.h>
+ #include <drm/drm_edid.h>
+
+-#include <linux/gcd.h>
+-
+ static void avivo_crtc_load_lut(struct drm_crtc *crtc)
+ {
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+@@ -801,57 +799,66 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
+ }
+
+ /* avivo */
++static void avivo_get_fb_div(struct radeon_pll *pll,
++ u32 target_clock,
++ u32 post_div,
++ u32 ref_div,
++ u32 *fb_div,
++ u32 *frac_fb_div)
++{
++ u32 tmp = post_div * ref_div;
+
+-/**
+- * avivo_reduce_ratio - fractional number reduction
+- *
+- * @nom: nominator
+- * @den: denominator
+- * @nom_min: minimum value for nominator
+- * @den_min: minimum value for denominator
+- *
+- * Find the greatest common divisor and apply it on both nominator and
+- * denominator, but make nominator and denominator are at least as large
+- * as their minimum values.
+- */
+-static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
+- unsigned nom_min, unsigned den_min)
++ tmp *= target_clock;
++ *fb_div = tmp / pll->reference_freq;
++ *frac_fb_div = tmp % pll->reference_freq;
++
++ if (*fb_div > pll->max_feedback_div)
++ *fb_div = pll->max_feedback_div;
++ else if (*fb_div < pll->min_feedback_div)
++ *fb_div = pll->min_feedback_div;
++}
++
++static u32 avivo_get_post_div(struct radeon_pll *pll,
++ u32 target_clock)
+ {
+- unsigned tmp;
+-
+- /* reduce the numbers to a simpler ratio */
+- tmp = gcd(*nom, *den);
+- *nom /= tmp;
+- *den /= tmp;
+-
+- /* make sure nominator is large enough */
+- if (*nom < nom_min) {
+- tmp = (nom_min + *nom - 1) / *nom;
+- *nom *= tmp;
+- *den *= tmp;
++ u32 vco, post_div, tmp;
++
++ if (pll->flags & RADEON_PLL_USE_POST_DIV)
++ return pll->post_div;
++
++ if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
++ if (pll->flags & RADEON_PLL_IS_LCD)
++ vco = pll->lcd_pll_out_min;
++ else
++ vco = pll->pll_out_min;
++ } else {
++ if (pll->flags & RADEON_PLL_IS_LCD)
++ vco = pll->lcd_pll_out_max;
++ else
++ vco = pll->pll_out_max;
+ }
+
+- /* make sure the denominator is large enough */
+- if (*den < den_min) {
+- tmp = (den_min + *den - 1) / *den;
+- *nom *= tmp;
+- *den *= tmp;
++ post_div = vco / target_clock;
++ tmp = vco % target_clock;
++
++ if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
++ if (tmp)
++ post_div++;
++ } else {
++ if (!tmp)
++ post_div--;
+ }
++
++ if (post_div > pll->max_post_div)
++ post_div = pll->max_post_div;
++ else if (post_div < pll->min_post_div)
++ post_div = pll->min_post_div;
++
++ return post_div;
+ }
+
+-/**
+- * radeon_compute_pll_avivo - compute PLL paramaters
+- *
+- * @pll: information about the PLL
+- * @dot_clock_p: resulting pixel clock
+- * fb_div_p: resulting feedback divider
+- * frac_fb_div_p: fractional part of the feedback divider
+- * ref_div_p: resulting reference divider
+- * post_div_p: resulting reference divider
+- *
+- * Try to calculate the PLL parameters to generate the given frequency:
+- * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
+- */
++#define MAX_TOLERANCE 10
++
+ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ u32 freq,
+ u32 *dot_clock_p,
+@@ -860,123 +867,53 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ u32 *ref_div_p,
+ u32 *post_div_p)
+ {
+- unsigned fb_div_min, fb_div_max, fb_div;
+- unsigned post_div_min, post_div_max, post_div;
+- unsigned ref_div_min, ref_div_max, ref_div;
+- unsigned post_div_best, diff_best;
+- unsigned nom, den, tmp;
+-
+- /* determine allowed feedback divider range */
+- fb_div_min = pll->min_feedback_div;
+- fb_div_max = pll->max_feedback_div;
+-
+- if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
+- fb_div_min *= 10;
+- fb_div_max *= 10;
+- }
++ u32 target_clock = freq / 10;
++ u32 post_div = avivo_get_post_div(pll, target_clock);
++ u32 ref_div = pll->min_ref_div;
++ u32 fb_div = 0, frac_fb_div = 0, tmp;
+
+- /* determine allowed ref divider range */
+ if (pll->flags & RADEON_PLL_USE_REF_DIV)
+- ref_div_min = pll->reference_div;
+- else
+- ref_div_min = pll->min_ref_div;
+- ref_div_max = pll->max_ref_div;
++ ref_div = pll->reference_div;
+
+- /* determine allowed post divider range */
+- if (pll->flags & RADEON_PLL_USE_POST_DIV) {
+- post_div_min = pll->post_div;
+- post_div_max = pll->post_div;
+- } else {
+- unsigned target_clock = freq / 10;
+- unsigned vco_min, vco_max;
+-
+- if (pll->flags & RADEON_PLL_IS_LCD) {
+- vco_min = pll->lcd_pll_out_min;
+- vco_max = pll->lcd_pll_out_max;
+- } else {
+- vco_min = pll->pll_out_min;
+- vco_max = pll->pll_out_max;
++ if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
++ avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
++ frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
++ if (frac_fb_div >= 5) {
++ frac_fb_div -= 5;
++ frac_fb_div = frac_fb_div / 10;
++ frac_fb_div++;
+ }
+-
+- post_div_min = vco_min / target_clock;
+- if ((target_clock * post_div_min) < vco_min)
+- ++post_div_min;
+- if (post_div_min < pll->min_post_div)
+- post_div_min = pll->min_post_div;
+-
+- post_div_max = vco_max / target_clock;
+- if ((target_clock * post_div_max) > vco_max)
+- --post_div_max;
+- if (post_div_max > pll->max_post_div)
+- post_div_max = pll->max_post_div;
+- }
+-
+- /* represent the searched ratio as fractional number */
+- nom = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? freq : freq / 10;
+- den = pll->reference_freq;
+-
+- /* reduce the numbers to a simpler ratio */
+- avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
+-
+- /* now search for a post divider */
+- if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
+- post_div_best = post_div_min;
+- else
+- post_div_best = post_div_max;
+- diff_best = ~0;
+-
+- for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
+- unsigned diff = abs(den - den / post_div * post_div);
+- if (diff < diff_best || (diff == diff_best &&
+- !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
+-
+- post_div_best = post_div;
+- diff_best = diff;
++ if (frac_fb_div >= 10) {
++ fb_div++;
++ frac_fb_div = 0;
+ }
+- }
+- post_div = post_div_best;
+-
+- /* get matching reference and feedback divider */
+- ref_div = max(den / post_div, 1u);
+- fb_div = nom;
+-
+- /* we're almost done, but reference and feedback
+- divider might be to large now */
+-
+- tmp = ref_div;
+-
+- if (fb_div > fb_div_max) {
+- ref_div = ref_div * fb_div_max / fb_div;
+- fb_div = fb_div_max;
+- }
+-
+- if (ref_div > ref_div_max) {
+- ref_div = ref_div_max;
+- fb_div = nom * ref_div_max / tmp;
+- }
+-
+- /* reduce the numbers to a simpler ratio once more */
+- /* this also makes sure that the reference divider is large enough */
+- avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
+-
+- /* and finally save the result */
+- if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
+- *fb_div_p = fb_div / 10;
+- *frac_fb_div_p = fb_div % 10;
+ } else {
+- *fb_div_p = fb_div;
+- *frac_fb_div_p = 0;
++ while (ref_div <= pll->max_ref_div) {
++ avivo_get_fb_div(pll, target_clock, post_div, ref_div,
++ &fb_div, &frac_fb_div);
++ if (frac_fb_div >= (pll->reference_freq / 2))
++ fb_div++;
++ frac_fb_div = 0;
++ tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
++ tmp = (tmp * 10000) / target_clock;
++
++ if (tmp > (10000 + MAX_TOLERANCE))
++ ref_div++;
++ else if (tmp >= (10000 - MAX_TOLERANCE))
++ break;
++ else
++ ref_div++;
++ }
+ }
+
+- *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
+- (pll->reference_freq * *frac_fb_div_p)) /
+- (ref_div * post_div * 10);
++ *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
++ (ref_div * post_div * 10);
++ *fb_div_p = fb_div;
++ *frac_fb_div_p = frac_fb_div;
+ *ref_div_p = ref_div;
+ *post_div_p = post_div;
+-
+- DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
+- freq, *dot_clock_p, *fb_div_p, *frac_fb_div_p,
+- ref_div, post_div);
++ DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
++ *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
+ }
+
+ /* pre-avivo */
