pll_1.diff (1257B)
1 commit 72edd83cc9e5819ed1ee771519143d7594e059f0 2 Author: Christian König <christian.koenig@amd.com> 3 Date: Thu Jan 29 16:01:03 2015 +0100 4 5 drm/radeon: fix PLLs on RS880 and older v2 6 7 This is a workaround for RS880 and older chips which seem to have 8 an additional limit on the minimum PLL input frequency. 9 10 v2: fix signed/unsigned warning 11 12 bugs: 13 https://bugzilla.kernel.org/show_bug.cgi?id=91861 14 https://bugzilla.kernel.org/show_bug.cgi?id=83461 15 16 Signed-off-by: Christian König <christian.koenig@amd.com> 17 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 18 Cc: stable@vger.kernel.org 19 20 diff --git b/drivers/gpu/drm/radeon/radeon_display.c a/drivers/gpu/drm/radeon/radeon_display.c 21 index 913fafa597ad..102116902a07 100644 22 --- b/drivers/gpu/drm/radeon/radeon_display.c 23 +++ a/drivers/gpu/drm/radeon/radeon_display.c 24 @@ -960,9 +960,6 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, 25 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 26 pll->flags & RADEON_PLL_USE_REF_DIV) 27 ref_div_max = pll->reference_div; 28 - else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 29 - /* fix for problems on RS880 */ 30 - ref_div_max = min(pll->max_ref_div, 7u); 31 else 32 ref_div_max = pll->max_ref_div; 33