pll_6.diff (1806B)
1 commit f8a2645ecede4eaf90b3d785f2805c8ecb76d43e 2 Author: Christian König <christian.koenig@amd.com> 3 Date: Wed Apr 16 11:54:21 2014 +0200 4 5 drm/radeon: improve PLL params if we don't match exactly v2 6 7 Otherwise we might be quite off on older chipsets. 8 9 v2: keep ref_div minimum 10 11 Signed-off-by: Christian König <christian.koenig@amd.com> 12 13 diff --git b/drivers/gpu/drm/radeon/radeon_display.c a/drivers/gpu/drm/radeon/radeon_display.c 14 index 063d4255137f..2f42912031ac 100644 15 --- b/drivers/gpu/drm/radeon/radeon_display.c 16 +++ a/drivers/gpu/drm/radeon/radeon_display.c 17 @@ -865,7 +865,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, 18 unsigned post_div_min, post_div_max, post_div; 19 unsigned ref_div_min, ref_div_max, ref_div; 20 unsigned post_div_best, diff_best; 21 - unsigned nom, den; 22 + unsigned nom, den, tmp; 23 24 /* determine allowed feedback divider range */ 25 fb_div_min = pll->min_feedback_div; 26 @@ -941,23 +941,22 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, 27 ref_div_max = min(210 / post_div, ref_div_max); 28 29 /* get matching reference and feedback divider */ 30 - ref_div = max(DIV_ROUND_CLOSEST(den, post_div), 1u); 31 - fb_div = DIV_ROUND_CLOSEST(nom * ref_div * post_div, den); 32 + ref_div = max(den / post_div, 1u); 33 + fb_div = nom; 34 35 /* we're almost done, but reference and feedback 36 divider might be to large now */ 37 38 - nom = fb_div; 39 - den = ref_div; 40 + tmp = ref_div; 41 42 if (fb_div > fb_div_max) { 43 - ref_div = DIV_ROUND_CLOSEST(den * fb_div_max, nom); 44 + ref_div = ref_div * fb_div_max / fb_div; 45 fb_div = fb_div_max; 46 } 47 48 if (ref_div > ref_div_max) { 49 ref_div = ref_div_max; 50 - fb_div = DIV_ROUND_CLOSEST(nom * ref_div_max, den); 51 + fb_div = nom * ref_div_max / tmp; 52 } 53 54 /* reduce the numbers to a simpler ratio once more */