commit 5d8be559bb9a31f8077253fc54f5062f0bb011f0
parent 8ae8e7b78aee4bd4829e65ff2d9e45137ef728dc
Author: Kyle Milz <krwmilz@gmail.com>
Date: Sat, 30 Apr 2022 18:56:55 +0000
update diffs for openbsd 7.1
Diffstat:
2 files changed, 38 insertions(+), 51 deletions(-)
diff --git a/imac_radeondrm_atombios_encoders.diff b/imac_radeondrm_atombios_encoders.diff
@@ -1,11 +1,11 @@
Index: radeon/atombios_encoders.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/radeon/atombios_encoders.c,v
-retrieving revision 1.15
-diff -u -p -r1.15 atombios_encoders.c
---- radeon/atombios_encoders.c 8 Jun 2020 04:48:15 -0000 1.15
-+++ radeon/atombios_encoders.c 18 Nov 2021 01:04:24 -0000
-@@ -2189,12 +2189,13 @@ int radeon_atom_pick_dig_encoder(struct
+retrieving revision 1.17
+diff -u -p -r1.17 atombios_encoders.c
+--- radeon/atombios_encoders.c 24 Feb 2022 12:49:47 -0000 1.17
++++ radeon/atombios_encoders.c 23 Apr 2022 18:13:00 -0000
+@@ -2187,12 +2187,13 @@ int radeon_atom_pick_dig_encoder(struct
}
/*
@@ -27,11 +27,11 @@ diff -u -p -r1.15 atombios_encoders.c
Index: radeon/radeon.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/radeon/radeon.h,v
-retrieving revision 1.26
-diff -u -p -r1.26 radeon.h
---- radeon/radeon.h 7 Jul 2021 02:38:37 -0000 1.26
-+++ radeon/radeon.h 18 Nov 2021 01:04:24 -0000
-@@ -2682,6 +2682,7 @@ void r100_pll_errata_after_index(struct
+retrieving revision 1.27
+diff -u -p -r1.27 radeon.h
+--- radeon/radeon.h 14 Jan 2022 06:53:15 -0000 1.27
++++ radeon/radeon.h 23 Apr 2022 18:13:00 -0000
+@@ -2711,6 +2711,7 @@ void r100_pll_errata_after_index(struct
(rdev->family == CHIP_RS740) || \
(rdev->family >= CHIP_R600))
#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
diff --git a/imac_radeondrm_display.diff b/imac_radeondrm_display.diff
@@ -1,11 +1,11 @@
Index: radeon/radeon_display.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/radeon/radeon_display.c,v
-retrieving revision 1.23
-diff -u -p -r1.23 radeon_display.c
---- radeon/radeon_display.c 19 Jul 2021 10:39:54 -0000 1.23
-+++ radeon/radeon_display.c 18 Nov 2021 00:59:11 -0000
-@@ -872,89 +872,66 @@ static bool radeon_setup_enc_conn(struct
+retrieving revision 1.24
+diff -u -p -r1.24 radeon_display.c
+--- radeon/radeon_display.c 14 Jan 2022 06:53:15 -0000 1.24
++++ radeon/radeon_display.c 23 Apr 2022 18:10:55 -0000
+@@ -864,76 +864,66 @@ static bool radeon_setup_enc_conn(struct
}
/* avivo */
@@ -17,16 +17,6 @@ diff -u -p -r1.23 radeon_display.c
+ u32 *frac_fb_div)
+{
+ u32 tmp = post_div * ref_div;
-+
-+ tmp *= target_clock;
-+ *fb_div = tmp / pll->reference_freq;
-+ *frac_fb_div = tmp % pll->reference_freq;
-+
-+ if (*fb_div > pll->max_feedback_div)
-+ *fb_div = pll->max_feedback_div;
-+ else if (*fb_div < pll->min_feedback_div)
-+ *fb_div = pll->min_feedback_div;
-+}
-/**
- * avivo_reduce_ratio - fractional number reduction
@@ -42,14 +32,21 @@ diff -u -p -r1.23 radeon_display.c
- */
-static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
- unsigned nom_min, unsigned den_min)
++ tmp *= target_clock;
++ *fb_div = tmp / pll->reference_freq;
++ *frac_fb_div = tmp % pll->reference_freq;
++
++ if (*fb_div > pll->max_feedback_div)
++ *fb_div = pll->max_feedback_div;
++ else if (*fb_div < pll->min_feedback_div)
++ *fb_div = pll->min_feedback_div;
++}
++
+static u32 avivo_get_post_div(struct radeon_pll *pll,
+ u32 target_clock)
{
- unsigned tmp;
+ u32 vco, post_div, tmp;
-+
-+ if (pll->flags & RADEON_PLL_USE_POST_DIV)
-+ return pll->post_div;
- /* reduce the numbers to a simpler ratio */
- tmp = gcd(*nom, *den);
@@ -61,6 +58,9 @@ diff -u -p -r1.23 radeon_display.c
- tmp = DIV_ROUND_UP(nom_min, *nom);
- *nom *= tmp;
- *den *= tmp;
++ if (pll->flags & RADEON_PLL_USE_POST_DIV)
++ return pll->post_div;
++
+ if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
+ if (pll->flags & RADEON_PLL_IS_LCD)
+ vco = pll->lcd_pll_out_min;
@@ -127,35 +127,18 @@ diff -u -p -r1.23 radeon_display.c
+ return post_div;
}
--/**
-- * radeon_compute_pll_avivo - compute PLL paramaters
-- *
-- * @pll: information about the PLL
-- * @dot_clock_p: resulting pixel clock
-- * fb_div_p: resulting feedback divider
-- * frac_fb_div_p: fractional part of the feedback divider
-- * ref_div_p: resulting reference divider
-- * post_div_p: resulting reference divider
-- *
-- * Try to calculate the PLL parameters to generate the given frequency:
-- * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
-- */
+#define MAX_TOLERANCE 10
+
- void radeon_compute_pll_avivo(struct radeon_pll *pll,
- u32 freq,
- u32 *dot_clock_p,
-@@ -963,138 +940,55 @@ void radeon_compute_pll_avivo(struct rad
+ /**
+ * radeon_compute_pll_avivo - compute PLL paramaters
+ *
+@@ -956,138 +946,55 @@ void radeon_compute_pll_avivo(struct rad
u32 *ref_div_p,
u32 *post_div_p)
{
- unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
- freq : freq / 10;
-+ u32 target_clock = freq / 10;
-+ u32 post_div = avivo_get_post_div(pll, target_clock);
-+ u32 ref_div = pll->min_ref_div;
-+ u32 fb_div = 0, frac_fb_div = 0, tmp;
-
+-
- unsigned fb_div_min, fb_div_max, fb_div;
- unsigned post_div_min, post_div_max, post_div;
- unsigned ref_div_min, ref_div_max, ref_div;
@@ -170,7 +153,11 @@ diff -u -p -r1.23 radeon_display.c
- fb_div_min *= 10;
- fb_div_max *= 10;
- }
--
++ u32 target_clock = freq / 10;
++ u32 post_div = avivo_get_post_div(pll, target_clock);
++ u32 ref_div = pll->min_ref_div;
++ u32 fb_div = 0, frac_fb_div = 0, tmp;
+
- /* determine allowed ref divider range */
if (pll->flags & RADEON_PLL_USE_REF_DIV)
- ref_div_min = pll->reference_div;
